XScale

microprocessor core, is Marvell's (formerly Intel's) implementation of the fifth generation of the ARM architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE (see more below). The PXA family was sold to Marvell Technology Group in June 2006[1].

The XScale architecture is based on the ARMv5TE ISA without the floating point instructions. XScale uses a seven-stage integer and an eight-stage memory superpipelined RISC architecture. It is the successor to the Intel StrongARM line of microprocessors and microcontrollers, which Intel acquired from DEC's Digital Semiconductor division as the side-effect of a lawsuit between the two companies. Intel used the StrongARM to replace their ailing line of outdated RISC processors, the i860 and i960.

All the generations of XScale are 32-bit ARMv5TE processors manufactured with a 0.18-µm or 0.13-µm (as in IXP43x parts) process and have a 32-KiB data cache and a 32-KiB instruction cache (this would be called a 64-KiB Level 1 cache on other processors). They also all have a 2-KiB mini-data cache.

Processor families

The XScale core is used in a number of microcontroller families manufactured by Intel and Marvell, notably:

* Application Processors (with the prefix PXA). There are four generations of XScale Application Processors, described below: PXA210/PXA25x, PXA26x, PXA27x, and PXA3xx.
* I/O Processors (with the prefix IOP)
* Network Processors (with the prefix IXP)
* Control Plane Processors (with the prefix IXC).
* Consumer Electronics Processors (with the prefix CE).

There are also standalone processors: the 80200 and 80219 (targeted primarily at PCI applications).

Intel i860

The Intel i860 (also 80860) was a RISC microprocessor from Intel, first released in 1989. The i860 was (along with the i960) one of Intel's first attempts at an entirely new, high-end instruction set since the failed Intel i432 from the 1980s. It was released with considerable fanfare, and obscured the release of the Intel i960 which many considered to be a better design. The i860 never achieved commercial success and the project was terminated in the mid-1990s.

Andy Grove blamed the i860's failure in the marketplace on Intel being stretched too thin:

“ We now had two very powerful chips that we were introducing at just about the same time: the 486, largely based on CISC technology and compatible with all the PC software, and the i860, based on RISC technology, which was very fast but compatible with nothing. We didn't know what to do. So we introduced both, figuring we'd let the marketplace decide. ... our equivocation caused our customers to wonder what Intel really stood for, the 486 or i860? ”

— Andy Grove,



Technical features

The i860 combined a number of features that were unique at the time, most notably its VLIW (Very Long Instruction Word) architecture and powerful support for high-speed floating point operations. The design mounted a 32-bit ALU along with a 64-bit FPU that was itself built in three parts, an adder, a multiplier, and a graphics processor. The system had separate pipelines for the ALU, floating point adder and multiplier, and could hand off up to three operations per clock. (I.e., two instructions - one integer instruction and one floating point multiply-and-accumulate instruction per clock.)

All of the buses were 64-bits wide, or wider. The internal memory bus to the cache, for instance, was 128-bits wide. Both units had thirty-two 32-bit registers, but the FPU used its set as sixteen 64-bit registers. Instructions for the ALU were fetched two at a time to use the full external bus. Intel always referred to the design as the "i860 64-Bit Microprocessor".

The graphics unit was unique for the era. It was essentially a 64-bit integer unit using the FPU registers. It supported a number of commands for SIMD-like instructions in addition to basic 64-bit integer math. Experience with the i860 influenced the MMX functionality later added to Intel's Pentium processors.

One unusual feature of the i860 was that the pipelines into the functional units were program-accessible, requiring the compilers to carefully order instructions in the object code to keep the pipelines filled. In traditional architectures these duties were handled at runtime by a scheduler on the CPU itself, but the complexity of these systems limited their application in early RISC designs. The i860 was an attempt to avoid this entirely by moving this duty off-chip into the compiler. This allowed the i860 to devote more room to functional units, improving performance. As a result of its architecture, the i860 could run certain graphics and floating point algorithms with exceptionally high speed, but its performance in general-purpose applications suffered and it was difficult to program efficiently

Intel i960

Intel's i960 (or 80960)was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field, along with the competing AMD 29000. In spite of its success, Intel dropped i960 marketing in the late 1990s as a side effect of a settlement with DEC in which Intel received the rights to produce the StrongARM CPU. The processor continues to be used in a few military applications.

Origin

The i960 design was started as a response to the failure of Intel's iAPX 432 design of the early 1980s. The iAPX 432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory — such as Ada and Lisp — in hardware. Because of its instruction-set complexity, its multi-chip implementation, and design flaws, the iAPX 432 was very slow in comparison to other processors of its time.

In 1984 Intel and Siemens started a joint project, ultimately called BiiN, to create a high-end fault-tolerant object-oriented computer system programmed entirely in Ada. Many of the original i432 team members joined this project, though a new lead architect was brought in from IBM, Glenford Myers. The intended market for the BiiN systems were high-reliability computer users such as banks, industrial systems and nuclear power plants.

Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The new design included a number of features to improve performance and avoid problems that had led to the downfall of the i432, which resulted in the i960 design. The first 960 processors entered the final stages of design, known as taping-out, in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986.

The BiiN effort eventually failed, due to market forces, and the 960MX was left without a use. Myers attempted to save the design by outlining several subsets of the full capability architecture created for the BiiN system. He tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and i386 (which taped-out the same month as the first i960), as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs's for use in the NeXT system. Competition within and outside of Intel came not only from the i386 camp, but also from the i860 processor, yet another RISC processor design emerging within Intel at the time.

Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems. The protected-memory architecture was considered proprietary to BiiN and wasn't mentioned in the product literature, leading many to wonder why the i960MX was so large and had so many pins labeled "no connect".

Intel iAPX 432

The Intel iAPX 432 was Intel's first 32-bit microprocessor design, introduced in 1981 as a set of three integrated circuits. The iAPX 432 was intended to be Intel's major design for the 1980s, implementing many advanced multitasking and memory management features in hardware, which led them to refer to the design as the Micromainframe.

The processor's data structure support allowed modern operating systems to be implemented on it using far less program code than ordinary processors, as the 432 did much of the work in hardware. The design also directly supported object oriented programming and garbage collection and was therefore much more complex than most processors of the era. Using the semiconductor technology of its day, Intel's engineers weren't able to translate the design into a very efficient implementation. Along with very weak early (PL/M and Ada) compilers, this contributed to slow but expensive computer systems. Intel's plans to replace the x86 architecture with the iAPX 432 thus ended miserably.

The abbreviation iAPX prefixing the model name reportedly stands for intel Advanced Processor architecture, the X coming from the Greek letter Chi.

The iAPX 432 was originally planned to have a clock speed of 10 MHz, but the available models were actually 5, 7, and 8 MHz.It operated at a top speed of 2 million instructions per second.

Development

The 432 project started in 1975 as the 8800, so named as a follow-on to the existing 8008 and 8080 CPUs. The design was intended to be purely 32-bit from the outset, and be the backbone of Intel's processor offerings in the 1980s. As such it was to be considerably more powerful and complex than their existing "simple" offerings. However the design was well beyond the capabilities of the existing process technology of the era, and had to be split into several individual chips.

The core of the design was the two-chip General Data Processor (GDP) which was the main processor. The GDP was split in two, one chip (the 43201) handling the fetching and decoding of the instructions, the other (the 43202) executing them. Most systems would also include the 43203 Interface Processor (IP) which operated as a channel controller for I/O. The two-chip GDP had a combined count of approximately 97,000 transistors while the single chip IP had approximately 49,000, making them some of the largest IC designs of the era. By way of comparison, the Motorola 68000 (introduced in 1979) had approximately 40,000 transistors.

In 1983 Intel released two additional integrated circuits for the iAPX 432 Interconnect Architecture, the 43204 Bus Interface Unit (BIU) and 43205 Memory Control Unit (MCU). These chips allowed for nearly glueless multiprocessor systems with up to 63 nodes.


The project's failures

Several design features of the iAPX 432 conspired to make it much slower than it could have been. The two-chip implementation of the GDP limited it to the speed of the motherboard's electrical wiring, although this is a minor issue. The lack of reasonable caches was more serious. The instruction set also used bit-aligned variable-length instructions (as opposed to the byte or word-aligned semi-fix formats used in the majority of computer designs), making instruction decoding quite complex. In addition the BIU was designed to support fault-tolerant systems, and in doing so added considerable overhead to the bus, with up to 40% of the bus time in wait states.

Post-project research suggested that the biggest problem was in the compiler, which used high-cost "general" instructions in every case, instead of high-performance simpler ones where it would have made sense. For instance the iAPX 432 included a very expensive inter-module procedure call instruction, which the compiler used for all calls, despite the existence of much faster branch and link instructions. Another very slow call was enter_environment, which set up the memory protection. The compiler ran this for every single variable in the system, even though the vast majority were running inside an existing environment and didn't have to be checked. To make matters worse it always passed data to and from procedures by value rather than by reference, requiring huge memory copies in many cases.


Impact and similar designs

An outcome of the failure of the 432 was that microprocessor designers concluded that object support in the chip leads to a complex design that will invariably run slowly, and the 432 was often cited as a counter-example by proponents of RISC designs. However it is held by some that the OO support was not the primary problem with the 432 and that the implementation shortcomings mentioned above would have made any chip design slow. Since the iAPX 432 there has been only one other attempt at a similar design, the Rekursiv processor, although the INMOS Transputer's process support was similar — and very fast.

Intel had spent considerable time, money and mindshare on the 432, had a skilled team devoted to it, and were loath to abandon it entirely after its failure in the marketplace. A new architect, Glenford Myers, was brought in to produce an entirely new architecture and implementation for the core processor, which would be built in a joint Intel/Siemens project (later BiiN), resulting in the i960-series processors. The i960 RISC subset became popular for a time in the embedded processor market, but the high-end 960MC and the tagged-memory 960MX were marketed only for military applications and saw even less use than the 432.