
Extensions
* Instruction Set expanded to 60 instructions
* Program memory expanded to 8 KB
* Registers expanded to 24
* Subroutine stack expanded to 7 levels deep
Designers
Federico Faggin proposed the project, formulated the architecture and led the design. The detailed design was done by Tom Innes.
New support chips
* 4201 - Clock Generator 500 to 740 kHz using 4 to 5.185 MHz crystals
* 4308 - 1 KB ROM
* 4207 - General Purpose byte Output port
* 4209 - General Purpose byte Input port
* 4211 - General Purpose byte I/O port
* 4289 - Standard Memory Interface (replaces 4008/4009)
* 4702 - 256 byte UVEPROM
* 4316 - 2 KB ROM
* 4101 - 256 4-bit word RAM
New features
* Interrupt
* Single Step
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